1. Field of the Invention
The present invention relates to a semiconductor memory device generating a start timing signal of a sense amplifier circuit, using a replica circuit including replica cells having the same configuration as that of memory cells included in a memory array.
2. Description of the Related Art
There are a number of methods for generating a timing signal of a sense amplifier for amplifying data read from memory cells and allowing a read timing of the memory cells to follow the variation due to a process, a voltage, or the like in a conventional semiconductor memory device. Among them, there is a method for varying a timing signal in a programmable manner, using a replica circuit. Hereinafter, this method will be described.
FIG. 11 is a functional block diagram (see U.S. Pat. No. 6,172,925) showing an exemplary configuration of a conventional semiconductor memory device. In FIG. 11, the conventional semiconductor memory device includes an SRAM memory array (hereinafter, merely referred to as a “memory array”) 900, a row decoder 901 connected to the memory array 900, a replica control circuit 902, sense amplifier circuits 903 connected to the memory array 900 and the row decoder 901, a replica circuit 904 controlled by the replica control circuit 902, and a sense amplifier control circuit 905 for controlling the sense amplifier circuits 903, connected to the replica circuit 904. Reference numeral 906 denotes SRAM memory cells (hereinafter, merely referred to as “memory cells”) constituting the memory array 900.
As shown in FIG. 11, the memory cells 906 are connected to word lines WL0 to WLx that are output signal lines of the row decoder 901 in a row direction, and connected to common bit lines BL, BB in a column direction.
FIG. 12 is a circuit diagram showing an internal configuration of the memory cell 906 shown in FIG. 11. In FIG. 12, the memory cell 906 includes an N-type transistor NA1 having a gate connected to a word line WL and a source connected to a bit line BL, an N-type transistor NA2 having a gate connected to the word line WL and a source connected to a bit line BB, a P-type transistor PL1 having a source supplied with a supply voltage VDD and a drain connected to a drain of the N-type transistor NA1, an N-type transistor ND1 having a gate connected to a gate of the P-type transistor PL1, a drain connected to the drain of the P-type transistor PL1, and a source connected to a ground potential VSS, a P-type transistor PL2 having a gate connected to the drain of the N-type transistor NA1, a source supplied with the supply voltage VDD, and a drain connected to a drain of the N-type transistor NA2, and an N-type transistor ND2 having a gate connected to the gate of the P-type transistor PL2, a drain connected to the drain of the P-type transistor PL2, and a source connected to a ground potential VSS.
Herein, the P-type transistor PL1 and the N-type transistor ND1 constitute a first inverter. The p-type transistor PL2 and the N-type transistor ND2 constitute a second inverter. An input terminal and an output terminal of the first inverter are connected respectively to an output terminal and an input terminal of the second inverter, whereby a latch circuit is configured.
FIG. 13 is a block diagram showing an internal configuration and a connection relationship of the replica circuit 904 shown in FIG. 11. In FIG. 13, reference numeral 907 denotes a replica word line (RWL) for driving the replica circuit 904, 908 denotes a replica bit line (RBL) connected to replica cells 909, 909 denotes replica cells (RMC), 910 denotes a selection line (SL1) for selecting one replica cell 909, 911 denotes a selection line (SL2) for selecting two replica cells 909, and 912 denotes a selection line (SL4) for selecting four replica cells 909.
As shown in FIG. 13, the word lines WL of the replica cells 909 are commonly connected to the replica word line 907 for driving the replica cells 909. One bit line BL of each replica cell 909 is connected to the selection line 910, 911, or 912 for selecting the replica cells 909. The other bit line BB of each replica cell 909 is connected to the replica bit line 908.
FIG. 14 is a circuit diagram showing an internal configuration of the replica cell 909 shown in FIG. 13. In FIG. 14, the transistors constituting the replica cell 909 have the same size as that of the transistors constituting the memory cell 906 shown in FIG. 12. In the latch circuit included in the replica cell 909, the first inverter composed of the P-type transistor PL1 and the N-type transistor ND1 is electrically insulated, and the second inverter composed of the P-type transistor PL2 and the N-type transistor ND2 has its output level fixed to a High level.
Next, an operation of a conventional semiconductor memory device configured as described above will be described. First, one of the word lines WL0 to WLx that are output signal lines of the row decoder 901 is selected, and data of the memory cells 906 are read to the bit lines BL, BB. The bit lines BL, BB and the replica bit line RBL are previously charged to a High level, and floated during selection of the word lines WL0 to WLx. There are a plurality of bit lines BL, BB, and a plurality of data are respectively read to the bit lines BL, BB.
The replica word line RWL that is an output signal line of the replica control circuit 902 is driven at substantially the same timing as that for selecting the word lines WL0 to WLx. Among n replica cells 909, transistors of the replica cells 909 selected by the selection lines 910 to 912 shift the signal level of the replica bit line RBL from a High level to a Low level at a speed that is n times that of the memory cells 906. The sense amplifier control circuit 905 detects the signal level of the replica bit line RBL, and generates a sense amplifier starting signal SAE. The sense amplifier starting signal SAE is input to the sense amplifier circuits 903, whereby the data of the bit lines BL, BB are amplified.
For example, it is assumed that the supply voltage VDD is 1.2 V, and it is desired to start the sense amplifier circuit 903 when a potential difference of data read from the memory cells 906 to the bit lines BL, BB is 100 mV In this case, if the number n of the replica cells 909 to be selected is set to be 6, the signal level of the replica bit line RBL is shifted to 600 mV (i.e., a half-value of the supply voltage VDD) at a desired sense amplifier start timing, and thus, the sense amplifier starting signal SAE can be generated by a simple CMOS gate without using a complicated potential detection circuit.
However, with the above-mentioned configuration of a semiconductor memory device, there are the following problems.
First, as the number of options regarding a start timing of the sense amplifier circuit 903 is increased, more replica cells 909 need to be provided. Furthermore, a new wiring region should be reserved even with respect to selection lines for selecting the replica cells 909. Consequently, a layout area is increased.